Quote:

damn, and just when I'm about to get one of these

http://www.hp.com/workstations/pws/xw6200/index.html

Yep. I've been looking over what is already there. No need to do work that's already done.

I was just mentioning a few higher level issues that will eventually have to be dealt with. That's the thing that probably puts off most people - whoever does this will have to go through every library, device, or whatever looking for where locking is needed. That isn't hard work, but it is tedious work. Missing one would possibly cause intermittent, hard to track down bugs.

It's why I haven't done anything with it yet. There are other easier things I can do yet before tackling this issue. Heck, I might be more likely to work on virtual memory before SMP.

well ive had some experience in this area, as little as it is.

My first step was to be able to find whats available (before attempting to second guess what would break from using smp)

Ive got the core of an acpi parsing table done though it isnt working properly atm since in my infinite wisdom i borked something =/

Anyhow, it was at the point of registering the "found" system information, apics, irqs, routing etc - which is where i got a bit lost to be honest.

Most things dont have addequate support in aros yet to function (ie youll need to fix irq.hidd etc to work properly with an acpi aware system).

It did however retrieve the info and register found processors with my cpu resource (the smp backbone if you like) - verified on my own SMP rigs and using BOCHS in upto 8way emulation.

I would recommend taking this route first - then identify and fix the locking/blocking issues that are encountered...

I've got a dual Celeron ABit BP6 I want to play around with SMP on when I get the chance. It'll be awhile, but I'd like to take a stab at MP on AROS. It seems to me that at least to start, you need to change Forbid/Permit/Disable/Enable functions (get rid of any macros for them), and add locking around libraries/devices updating their structures.

Yes, but only on a single "core"

Dual core technology from a developer/os point of view works like any other smp hardware using intel defined structures.

Supporting dual (*or more ) cores would mean supporting SMP in general..

With Dual Cores coming up, will AROS run on them at all?

Dammy